//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OPBWait.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "PICO" project                     ////
////  http://www.picocomputing.com                                ////
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////                                                              ////
//////////////////////////////////////////////////////////////////////
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//// Copyright (C) 2004, Pico Computing, Inc.                     ////
//// http://www.picocomputing.com                                 ////
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//// This source file is free software; you can redistribute it   ////
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////////////////////////////////////////////////////////////////////DH

/*
 * this module will wait the amount of clock cycles specified in OPB_WAIT_CYCLES
 * to assert Sl_xferAck as long as opb_en is asserted
 */
module OPBWait(opb_en, OPB_Clk, OPB_Rst, Sl_xferAck);

parameter OPB_WAIT_CYCLES = 15;

input opb_en;
input OPB_Clk;
input OPB_Rst;
output Sl_xferAck;

reg [OPB_WAIT_CYCLES-1:0] ack_wait;
assign Sl_xferAck = ack_wait[0];

/* start up our shift register when opb_en is asserted and ack_wait is all zeros */
wire start_wait = (~|ack_wait) & opb_en;

always @(posedge OPB_Clk) begin
   if(OPB_Rst)                // reset shift register if we get an opb reset
      ack_wait <= 0;
   else if(start_wait)        // start up wait state generator
      ack_wait <= { 1'b1, {OPB_WAIT_CYCLES-1{1'b0}} };
   else if(opb_en)            // as long as opb_en is asserted, shift register
      ack_wait <= { 1'b0, ack_wait[OPB_WAIT_CYCLES-1:1] };
   else
      ack_wait <= 0;
end

endmodule
